This invention relates generally to integrated circuit (I.C.) computer component chips, and particularly to high performance chips.
The development of single integrated circuit chip microprocessors and microcomputers has been rapid since their initial introduction in the early 1970's. The first generation of such devices processed four bits of data at one time, followed quickly by an eight-bit processor. More recently, 16-bit processors have become commonly used, and 32-bit processors are coming to the market. One primary goal in the evolution of processors is to maximize their performance (i.e. the speed of operation, capability and flexibility to the user) on a single chip that is small enough that manufacturing yields of the chip are sufficiently high.
To further increase processor performance, separate dedicated processing chips are often provided in a system with a controlling microprocessor or microcomputer. The tasks to which the second processor is dedicated are thus performed extremely fast. A computer system designer can select a dedicated processor to perform one of several specific functions with high performance but without having to increase the size or complexity of the controlling microprocessor or microcomputer integrated circuit chip.
It is a primary object of the present invention to provide improved cooperative architecture of a central processing unit (CPU), the controlling master processor, and of an extended processing unit (EPU), the dedicated slave processor (co-processor), in a manner that improves overall performance of a computer system using such a combination.